Digital division by reciprocal conversion technique

ABSTRACT

A reciprocal conversion technique for obtaining the quotient of two numbers and the reciprocal of a number. A predetermined number of leading bits of the mantissa of the denominator is used as an entry into a table used for locating the required number of shifts and adds or shifts and subtracts to form a standard from of a denominator. Significant precision control and the semireciprocal of the normalized fraction is formed in successive multiplication steps. The reciprocal of the normalized fraction is formed and the quotient can thereafter be determined with a final multiplication step.

United States Patent Inventor Appl. No.

Filed Patented Assignee DIGITAL DIVISION BY RECIPROCAL [56] ReferencesCited UNITED STATES PATENTS 3,234,369 2/ 1966 Roth et a1. 235/ l 643,508,038 4/ l 970 Goldschmidt et al 235/164 Primary Examiner-Malcolm A.Morrison Assistant Examiner-.David H. Malzahn Attorneys-Hanifm andJancin and Peter R. Leal ABSTRACT: A reciprocal conversion technique forobtaining CONVERSION TECHNIQUE the quotient of two numbers and thereciprocal of a number. 5 Claims, 4 Drawing Figs. A predetermined numberof leading bits of the mantissa of the denominator is used as an entryinto a table used for locatin u.s. Cl 235 164 8 0 the required number ofshlfts and adds or shifts and subtracts to form a standard from of adenominator. Significant preci- Int. Cl 60 7/52 SlOI'l control and thesemireclprocal of the normalized fraction Field of Search 235/156,

164 IS formed in successive mult plication steps. The reciprocal of thenormalized fraction is formed and the quotient can thereafter bedetermined with a final multiplication step.

I30 R z s 200 300 sTo RE m j 501 ''r-G N ID 0 N 2 N DIV EN R 1g? m I T LNORMALIZATION T2 LOOK up LEFT JUSTIFICATION E T 128 502 50R 2 x iENTRIES m OlVI dm 0.d d 2 T 1 730 H T .4 4 4 ...d

4o0-- STANDARD ADDER BLOCK E LE L Q LQ LL BQEQM- Fwd-u SE I'IP:HE I FORTEMPORAR'LY STANDARD FORM 1 1' 2 1 6 5) 540 530% 3t 75% #515 GMMULTIPLIER 740x Q-R UNIT 700 l L E i L F 6m 602 FORM THE 7' QUOTIENTARESET I STANDARD FORM MR i fit iiz'iaa fi r I no no m 0F 0 FRACTION no.l I Q2,Q3 r Q I RECIPROCAL L fi Tso- 1 2 DIGITAL DIVISION BY RECIPROCALCONVERSION FIG. 4 is a representation of the formation of reciprocal aTECHNIQUE normalized fraction number 0.. and its relation with the resetBACKGROUND OF INVENTION procedure FIG 1. Field ofthe Invention 5DESCRIPTION OF PREFERRED EMBODIMENT This invention relates to a digitalcomputer: arithmetic undulyinS Theory unit, and more particularly todigital system and methods f An embodiment of my invention will bedescribed. In the obtaining the reciprocal ofa number and the quotientof two embodiment, the dividend and thfi dllVlSOI will both be I!-numbers malized, that is, justified such that the binary point of each2. Description ofPrior Art 10 number are aligned such that there is aone" in the high Division is an infinite process. In order to reduce theiteraorder of each number. The following description of the undertioncycle required to obtain the quotient in computers, many lying theory ofmy invention will be helpful in understanding methods have beenproposed. Among them, the multiple subthe embodiments to be described.While the invention is traction process was used in earlier machines,though it is de cribed with reference to the binary number system, itgenerally not in use today. The use of Newtons method as will berecognized by those of ordinary skill inthe art that the mentioned byRabinowitl (C C P- 1961) and Gollinvention can be implemented in othernumber system withlieb p Data Processing P- 5142) evaluating outdeparting from the spirit and the scope of the invention.

reciprocal of a number was extensively used in the early com- L N d D bh: numerator d denominator whose puters. The nonrestoring divisionmethod used in the Stretch 20 tient Q is being sought. (We note thatwith proper scaling, N P p pp y ls relatively slow- Recently Knuth inand D can be integers or even general floating-point numhis book Art ofComputer Programming, Seminumerical b Th Algorithms, Vol. II p. 275,Addison-Wesley Publishing Com- Q==N( l/D) (l) P 2 suggcsted a fastmultiplication routine to P Q Since l/D generally contains an infinitenumber of terms, it the f fl F due to qy q t p gi is necessary tocollect all the significant terms (commonly the initial approximation,and the varied iteration cycles, this known a precision) i h a i iamount f ff F method is not suitable for high-performance machines.Since ample, =1 14-1 where R is approximate reciprocal multiplicationcan be fast as mentioned by Andersons paper f n is the required number fi i bits.

( 101111181 P 11 1 P- 1967) One of the equation obtained in the earlypaper (the invenand by Llng S Presentatlon Computer Multlphcatlon torspresentation to the IEEE Workshop as mentioned above) gorithm andlmplefnematim" IEEE theory of allowing for multiplication to be handledby blocks, can also Computer Amhmet'c June 1969) has generally be usedto obtain the reciprocal of the denominator. Let

become the trend to express the division in terms of finite mul- 81:3 df(d) (2) tiplication steps. The latter presentation is documented in thewhere dis the mantissa of D publication on "High-Speed ComputerMultiplication using a (1:0 5 5 8 5 =1 2 Multiple Bit DecodingAlgorithm, by H. Ling, IBM Research 35 and fiJ Z wary) '1) Report, RJJune 1969- since, from equation (2.1 it is known that '6, is a l inbinary in The denominator quadratic convergence method as menh t tionedby Anderson, used in the IBM 360/91, and the 32,2221 g giiggg g ggfgixthe equation for dean be 360/ 195, is generally considered to be thebest method today. 0 M 1 a a 6 However, with the requirement of twohigh-speed multipliers 6 0 528 8 (one for the denominator, the other forthe numerator), one i=0 +0 H (2 3) requires four multiplies in parallelin order to obtain 32bit precision. Comparatively speaking, therefore,the method is 2:52:: Working m binary ls one'half so that can not fast.A faster and more flexible scheme 15 presented in this dcl /2 +1 ($283an) invention, and at a reduced hardware cost. or

SUMMARY OF THE INVENTION where ri -408,8 5, 6,) By substituting equation(3) into (2), we have My invention provides a reciprocal convergencetechnique 3 1 do) dc) for obtaining the quotient of the division and thereciprocal of r? f +3- (31) a number. Using 6 8 8 5 8 6 8 of the eightleading bit of the I v. 7M

- mantissa of the denominator as an entry to a table, the f( q i (2- a drequired number of right shift and Add or Subtract are stored atregisters MR(+) and MR(). After performing the required 1 dm shift andadd or shift and subtract, the standard form of the denominator isformed. The significant precision control array S, is formed with onesimple multiplication. The semireciprofrom equatwn then cal of anormalized fraction is formed with one more multipli- I 1 d cation,after reset stage, the reciprocal of a normalized frac- 1 d (5 7) 1 dd)tion is formed. The quotient of the division is formed with one f (ff?)T (5+ more multiplication. My invention can be used to find thereciprocal of a number (1 19) i 1 with two multiplications, and thequotient of two numbers 2 2 2 2 2 2 2 with three multiplications.Compared to the existing fastest w u methods, my invention shows notonly a gain in speed, but also so that equation (3, l b o a saving inhardware.

' S (ypLpfiQ) gszmiliflwEFL 1 BRIEF DESCRIPTION OFTHE DRAWINGSMultiplying both sides by 2 and simplifying:

FIG. I isadataflow diagram ofanimplementation ofmyin- (1 m) (1 1 gig)vention using the method of reciprocal convergence 2 2 2 2 2 2technique. 1 d 1 1 1 FIG. 2 is a representation of the procedure and the5 technique to obtain the standard from l+d of FIG. 1.

FIG. 3 is a representation of the procedure to obtain the (1 l(i) l 1 1+d precision significant number 5, ofFIG. 1. 2 2 3 From equation (2.2)above, it can be seen that the last term of equation (3.3) is equivalentto 1 .6 iffilL- so that equation (3.3) can be rewritten as 1L l l 2 l mm2 4 4: 2 Collecting terms and continuing, 2O

2S,=0.75 (H' m) '-O.5f(d (4) Dividing both side of equation (4) by l+dwe have 1 f( m) a 2 l but f(d )=d /2 l+d from (2.2) so that 23 1 1 m-lm) 2 (1+dm) or m 1 d T4 (4a) Let 2s,=3 2s, 2f(2S,) (5.1 2S =3(2S 2f(2S(5.2) 2S =3(2S 2f(2S (5.3) etc. By dividing equation (5.1) on both sidesby 1411 we obtain 2S; 3( S1) f( 5'1) But from (2.2 it is seen that f(1)=(( 1)/( 1) Therefore substituting (5.1b) into (5.1a) we have:

28 2S; 1 2 1 S m a m) 2 1) 2S. 2s, 2s1(2s1) -lm i- 2)) -im) 2S1:lifltnpg a i "HA w v sothat Substituting equation (4a) in equation (6.l we ha v e 2s. 1 1+d(2) (2 2 S1 By dividing equation (5.2) on bothsides by H-d and simplifying terms as was done for equation (6.1

m m 2) Substituting equation (6.1a) into equation (6.2) we have 2s. g 11 7i... 2 2 8128 muTtiplying both sides of (6. l by l-l-d $355378 7' v2S =2S 2S, so that S,=2S,S (6.20) by substituting (6.2a"), into (6.20 wehave l L l I 1 1+dm- 2 (a)) i SiS1 (62 a generalized equation of theabove form can be derived as but by inspection of (2.2) it is seen thatf(2S,,'.,)=S,, ,(1+2S,, (5.n2) Substituting (5.n2)

into(5.nl)we have But, as above, l-S,, ,]can be written as S,, so that28;; I 11-! I I 1+d l-l- (n) 1) Equation (6.1) to (6.2n) show that ifl+d hereinafter referred to as the standard form of the denominator, haseight leading ones in binary, then 28 is guaranteed to have 16 leadingones. Since S will have 8* 2P leading ones, when the precision n isspecified, P is automatically decided by n=l 6P. For example, if asingle precision 32-bit quotient is required, then S is selected. Sincel6-bit and 32-bit machines are most popular, the use of S is generallysufficient. Let us rewrite S and S in the following explicit form:

The above equation defines the first word approximation of thereciprocal of the normalized fraction for 16-bit precision.

The above equation defines the second order approximation of thereciprocal of the normalized fraction for 32-bit precision.

For larger machines, 64-bit double precision is sometimes needed andequation (6.2) can be written into the reciprocal of the normalizedfraction for 64-bit precision. For multiple precision equation (6.n)will generally apply.

gag-ass) TABLE IContlnued Leading S bits of the denominator Requirednumber of right d1=l always shift acids or subtracts d2 tie: d1 (is du(1 da 1 2 3 4 5 6 7 8 1 0 1 0 1 1 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 11 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 00 1 1 1 0 1 0 1 1 l- 1 1 0 1 1 0 1 1 1 0 1 1 a 1 l- 1 1 1 0 1 1 1 0 0 11 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 11 1 1 1 1 1 1 add again. Finally since the is three places away from theprevious entry, you shift three places and subtract. The results is thedesired eight leading ls. This information is used to form the standardform of 1+d Adder Block 400 and the standard fonn is also stored atregister MR,,(+) 301 and Referring now to FIG. 1 and 2, the data storedat the first adder 421 of the adder block 400 is controlled by MR,,(+)301, if the bit n of MR-(+) is on, the right shift and add takes place,1+d is incremented by 2 "(l +d and the sum is set to the next adder 422via the data bus 41 1. If bit n of the MR,,(-) is on, the right shiftand subtract takes place, the contents of 422 (l+d is sent to register423 via data bus 412 and also sent to third adder 424 via data bus 417.The leading bit of (H11 at register 423 is tested by any well-known zerotest apparatus ZT. If the leading bit LB of 423 is zero, the contents ofregister 423 are sent to register 425 via data bus 416 and is thestandard form of the denominator.

If the leading bit of (l+d is one, which represents that overfilling hasoccurred, the contents of the 423 are decremented by 2( l+d and theresult is sent to register 425 via data bus 414. The contents ofregister 425 is the Standard form of the denominator, l+d It is sent tothe precision control unit 500 of FIG. 3 via data bus 415.

Referring now to FIG. 1 and 3, the first entity of the precision controlunit is a shift register 500. The Precision Control Unit is used todevelop a Precision Control Number. If only 16-bit precision isrequired, the precision control number is .5. If greater than 16-bit(Le, 32, 64 is required, the Precision Control Unit should be used. Whenthe number of precision bits is specified sat 32 bits, the leading 32bits of the fraction portion d of register 500 is set to the multipliervia data bus 530, and to shift register 502 via data bus 511. Thecontents of 502 is right shifted 2 places with its leading 2 bits set toone by well-known means and set to adder 503. At the same time thecontents of 502 are complemented and I place right-shifted with itsinteger bit set equal to one and set to 602 of the reset stage via databus 520. In the multiplier, the leading 32 bits of the fraction portionof the contents of register 500 are multiplied by its own complement.The product is right shifted 2 places and sent to adder 503 via data bus540. The contents of adder 503 is added with this incoming data, theresults is set to a shift register 504 via data us 513. The contents ofregister 504 is right shifted 1 bit and complemented, the result isstored at register 505. The contents of 505 is called 8,, the PrecisionControl Number, and sent to the Reset Unit 600 via data bus 515. I

Referring now to FIGS. 1 and 4 there is seen the reset stage of myinvention. The contents of registers 600 and 602 are sent to themultiplier via data bus 630. The product Q decremented by 2 Q, if theleading bit of register 423 was on as indicated by enable line 437. Thisnew Q is called Q,,,, (i.e., Q, modified to take into account theoverfill situation) and is sent to the shift and adder 621 via data bus640. When the register MR,,(+) was on, the right shift and add takesplace, Q is incremented by Q ,,.2", and the result O is sent to the nextshift and adder 622 via data bus 611. If there was no overfill, theoutput can be gated by the complement of line 437 directly shift and addregister 621. If the MR,,( wason, O is decremented by 2"0 in 622.Theresult Q, is left shifted I place and set to register 623 via databus 612'. If MR,,() was off, the contents of 62] O is left shifted 1place and set to register 623 via data bus 615. These resets essentiallyreadjust the outputs 0 or Qru to take account of the originalmanipulation which was dictated by the table lookup to obtain thestandard form of the denominator. The contents of 623, O is thereciprocal of the normalized fraction number d,,,. In order to form thereciprocal of a number or the quotient of two numbers, O is sent to Q-Runit 700 via data bus 614. Referring now to FIG. 1, register R l00 heldthe normalized numerator's exponent and mantissa. The mantissa portionis sent to the multiplier via data bus 730, the exponent portion is sentto the quotient register 770 via data bus 750. Register R l01 held thenormalized numerators exponent and mantissa, the mantissa portion wasused to generate the reciprocal is sent to the reciprocal register 780via data line 760.

If only 16-bit precision were desired, the pass through the PrecisionControl Unit could have been eliminated and the contents of 602 couldhave been shifted right one place (i.e. S,=0.5) and used directly as aninput to 624 (if overfill occurred) or to 621 (if no overfill occurred).

The Q-R unit contains two shift registers, the Quotient register 770,and the Reciprocal register 780. The incoming data 0 has been sent totwo places, the multiplier via data bus 730 and the Reciprocal shiftregister 780. When the reciprocal of a number is requested, the contentsof register 780 is right shifted E places. The reciprocal of a number isthereby formed. When the quotient (Numerator/Denominator) is requested,the product of Q and the mantissa of the numerator is sent to thequotient register 770 via data bus 740, and the contents of Quotientregister is left shifted E the quantity (EV-ED) being formed by an addersuch as A associated with register 770. The quotient of the two numbersis thus formed.

EXAMPLE Find the Quotient of 2057/43701 with 32-bits precision. Inbinary, these numbers are represented as N =1 00000001001 D=10l0101010110101 After normalization-left justification,

holds register R E-=12 n 0. 10000000 1 00 I register R l0l holds E -16d,,,=

Since MR,.() is equal to zero, there is no operation in the second adder422 and (l+d is equal to (l+d )J and sent to register 423 for testingits leading bit. Since the leading bit of register 423 is on, (l+d iSSent to the third adder 424 via data bus 413. In adder 424, l-l-d isformed by decrementing (H112)! y H112)! l+d@, IS sent to register 425via data bus bus 414. After obtaining the standard form of l+d refer toFIGS. 1 and 3. Since the specified precision bits are 32 bits, theleading 32 bits of the fraction portion d namely:

0.1111111000011l10l1l0000l0000-0 are sent to the multiplier via bus 530,and also stored at register 502 via bus 511. The contents of 502 is thenright shifted 2 bits, with its leading 2 bits set to one. The number isthen,

(only 32 leading bits are taken) This data is right tow shifted bit andsent to adder 503. Adder 503 contains the following two numbers,

0.0000000001110111011001011011001010 0.11111111100001111011100001 2S isformed by adding these two numbers together, that is0.1111111111111111000111011111001010(only 32 leading bits are taken)This data is sent to shift register 5041 via data bus 513. The

contents of 504 is then right shifted 1 bit, complemented, and sent toregister 505 via data bus 514. The contents of register 505 is calledthe precision control number S Since the requested precision is 32 bits,the leading 32 bits of the contents of register 505 are,

This data is sent to register 600 of the Reset Unit via bus 515. Refernow to FIGS. 11 and 4. The contents of register 600 and 602 are shown asfollows:

These two data are set to the multiplier via data bus 630, the product Qis returned to shift and add register 624 via data bus 641. The product0 is equal to 0.1000000001111000101110010011000100 Since the leading bitLB of register M3 was on, Q, is subtracted by 2 O and the result Q,,,,is equal to 0.01111 111111110000100000001111000 (only 32 leading bitsare collected) Q is set to a shift and add register 621 via data bus640. Since MR was on, O is added with 2"Q and the result 0 is equal to0.101111111111010001100000101101000 Since MR,,() was off, therefore, (I-Q the contents of register 621 is right shifted 1 bit and sent toregister 623 via data line 615. The contents of register 623 is thereciprocal of the normalized fraction number 0., and is equal to Thisdata is sent to Q-R via data bus 614 to the reciprocal shift register780, and to the multiplier via data bus 730.

The reciprocal of d is obtained by shifting 0 right 16 bits. That is0.000000000000000101 111111111010001100000101101000 Which is000002288277 in decimal.

when the quotient of a division is requested, Q, along with n are sentto the multiplier via data bus 730. The product is returned to theQuotient register 770 via data bus 740. The product is equal to Thequotient is obtained by shifting this data left E E,, places, in thiscase, E-E,,equal to 4. Therefore, the shifting is toward the reversedirection, that is toward the right 4 places. The quotient of MD is0.000011000000110011000101001110100000110010101 which is 0047069861 1 indecimal.

As a time saving device, if it is determined, by well known testingmeans, that l+d already has 16 leading ones, then the Precision ControlUnit calculation can be skipped, thus saving one multiplication.

The above detailed example was for 32-bit precision. lf only 16-bitprecision were desired, the pass through the Precision Control Unitcould be eliminated as described above. On the other hand if N-32-bitprecision were desired, n passes through the Precision Control Unitshould be made before proceeding to the reset stage. This can be seen byequation 6.n.

Further, if only eight-bit precision were desired, only 4 leading zeroswould be required for the standard form 1.1 1 1 In this case the tablelookup could be replaced by a simple logic implementation based on thetable While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes inform and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. The method of obtaining electrical signals represent the reciprocalof a number D comprising the steps of:

l. calculating electrical signals representing the left justifiedmantissa of D, d,,,;

2. adjusting said electrical signals representing said justifiedmantissa to obtain electrical signals representing a standard form ofthe number containing a desired number of leading one bits, saidstandard form having a fraction portion 3. calculating electricalsignals representing a precision control number;

4. calculating electrical signals represent the quantity one pulseone-half the complement of said fraction portion of said standard form;

5. multiplying said electrical signals representing said quantity bysaid electrical signals representing said precision control number toobtain electrical signals representing the bits of the reciprocal to adesired precision; and

6. shifting said electrical signals representing the bits of thereciprocal to account for the original left justification of saidmantissa.

2. The method of claim 1 further including the step of multiplying saidshifted electrical signals representing the bits of the reciprocal by anumber N to obtain the quotient of N divided by D.

3. Apparatus for obtaining the reciprocal of a left-justified number D,comprising in combination;

inspection means for inspecting certain bits of the mantissa d,,, ofsaid number D and supplying information defining the mathematicalcalculation necessary to transform said mantissa into a standard formhaving a desired number of leading 1 bits, said standard form having afraction portion;

first arithmetic means connected to said inspection means, includingshift and addition means, for performing said defined mathematicalcalculation on said mantissa;

precision control means connected to said first arithmetic means forcalculating a precision control number as a function of said standardform;

said arithmetic means for calculating the quantity one plus one-half thecomplement of the fraction portion of the standard form; and

multiplication means for multiplying said precision control number bythe quantity one pulse one-half the complement of the fraction portionof the standard form to obtain the bits of the reciprocal to the desiredprecision.

4 The combination of claim 3 further including means for 5. Th6combination of claim 3 further including means for adjusting said bitsof said reciprocal to account for said left l iply ng 8 number N y theit of th reciprocal to obtain justification to obtairi the desiredreciprocal. the quotient MD- P1050 UNITED STATES PATENT OFFICECERTIFICATE OF CORRECTION Patent No. 018 Dated January 4, 1972 t -(8)Huei Ling It is certified that error appears in the above-identifiedpatent and that said Letters Patent are hereby corrected as shown below:

Pool. 2, line 42, the portion of the equation "(.6 b2 6 6 should "1 read6 z 6 3 6 line 48, after 5 insert Col. 3, line 22, the portion of theequation"[f(d should read [f(d line 33, the portion of the equation "(d(should read -f(d 2 line 50, "(2. 2" should read --(2. Z)--; after line66 the following equation, should appear: 2 S1 ZS fWhere s ':1-s (6.1

1+d l d Col. 4, after line 2, insert --We obtain:--; line 23, theportion of the equation "(1+d should read --(l+d line 47, "Equation"should be --Equations line 70, "Written" should be --rewritten.

Col. 8, line 55, "1+ should read --l+d line 56 "(1+d The" should 2 2 2read ---(l+d The--. to

line 3 0, Col. 9,Aafter the final 1 add --l--; line 32, 'set" should be--sent--; line 41, 'set" should be --sen1:--.

C01. 10, line 28, "represent" should be --representing--; line 40,"represent" should be --representing.

Signed and sealed this th day of July 1972.

(SEAL) Attest:

EDwARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents

1. The method of obtaining electrical signals representing thereciprocal of a number D comprising the steps of:
 1. calculatingelectrical signals representing the left justified mantissa of D, dm; 2.adjusting said electrical signals representing said justified mantissato obtain electrical signals representing a standard form of the numbercontaining a desired number of leading one bits, said standard formhaving a fraction portion;
 3. calculating electrical signalsrepresenting a precision control number;
 4. calculating electricalsignals represent the quantity one pulse one-half the complement of saidfraction portion of said standard form;
 5. multiplying said electricalsignals representing said quantity by said electrical signalsrepresenting said precision control number to obtain electrical signalsrepresenting the bits of the reciprocal to a desired precision; and 6.shifting said electrical signals representing the bits of the reciprocalto account for the original left justification of said mantissa. 2.adjusting said electrical signals representing said justified mantissato obtain electrical signals representing a standard form of the numbercontaining a desired number of leading one bits, said standard formhaving a fraction portion;
 2. The method of claim 1 further includingthe step of multiplying said shifted electrical signals representing thebits of the reciprocal by a number N to obtain the quotient of N dividedby D.
 3. Apparatus for obtaining the reciprocal of a left-justifiednumber D, comprising in combination; inspEction means for inspectingcertain bits of the mantissa dm of said number D and supplyinginformation defining the mathematical calculation necessary to transformsaid mantissa into a standard form having a desired number of leading 1bits, said standard form having a fraction portion; first arithmeticmeans connected to said inspection means, including shift and additionmeans, for performing said defined mathematical calculation on saidmantissa; precision control means connected to said first arithmeticmeans for calculating a precision control number as a function of saidstandard form; said arithmetic means for calculating the quantity oneplus one-half the complement of the fraction portion of the standardform; and multiplication means for multiplying said precision controlnumber by the quantity one pulse one-half the complement of the fractionportion of the standard form to obtain the bits of the reciprocal to thedesired precision.
 3. calculating electrical signals representing aprecision control number;
 4. calculating electrical signals representthe quantity one pulse one-half the complement of said fraction portionof said standard form;
 4. The combination of claim 3 further includingmeans for adjusting said bits of said reciprocal to account for saidleft justification to obtain the desired reciprocal.
 5. The combinationof claim 3 further including means for multiplying a number N by thebits of the reciprocal to obtain the quotient N/D.
 5. multiplying saidelectrical signals representing said quantity by said electrical signalsrepresenting said precision control number to obtain electrical signalsrepresenting the bits of the reciprocal to a desired precision; and 6.shifting said electrical signals representing the bits of the reciprocalto account for the original left justification of said mantissa.